Re: [BLACKBOX] Project Oberon - FPGA

From: [at]} <Chris>
Date: Sun, 19 Feb 2012 08:38:46 +1030

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>-----Original Message-----
>From: BlackBox [mailto:BLACKBOX{([at]})nowhere.xy
>Wojtek Skulski
>Sent: Sunday, 19 February 2012 8:28 AM
>To: BLACKBOX{([at]})nowhere.xy
>Subject: Re: [BLACKBOX] Project Oberon - Oberon day videos
>
>> Yes. Niklaus Wirth and Paul Reed have implemented it on Wirth's own
>> RISC computer design which has been implemented on FPGA,
>using Verilog
>> on a Xilinx Spartan-3 development board. They also have it
>running on
>> a virtualised PC.
>
>It starts being interesting. One of outstanding problems with
>FPGA "programming" (which is not programming at all) is a high
>level of difficulty for average mortals. One of the solutions
>is embedding a processor core inside the FPGA and cast the
>problem back into the sequential domain. The problem is, that
>this solution is quickly evolving into a nightmare of its own.
>Perhaps Wirth with his "make it as simple as possible, but no
>simpler" has found a proper balance?
>
>I am using Spartan-6 in my designs. So it may be relevant.
>

Having spent the past few months up to my neck in the bizarre convoluted
details of the Cortex-M3 instruction encoding it would be sheer delight to
work with his RISC design. Wirth's advantage is that he does not (need to)
let backward compatibility get in the way of progress.

More details of his FPGA work and the Verilog sources are here:

http://www.inf.ethz.ch/personal/wirth/Articles/FPGA-relatedWork/index.html

Regards,
Chris

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Received on Sat Feb 18 2012 - 23:08:46 UTC