Re: [BLACKBOX] Project Oberon - FPGA

From: [at]} <Wojtek>
Date: Sat, 18 Feb 2012 19:38:33 -0500

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> Yes. Niklaus Wirth and Paul Reed have implemented it on Wirth's
> own RISC computer design which has been implemented on FPGA,
> using Verilog on a Xilinx Spartan-3 development board.
> http://www.inf.ethz.ch/personal/wirth/Articles/FPGA-relatedWork/index.html

I read the NW report. According to the body of the report they used ML-505
which is a Virtex 5 LXT eval board. In the reference section they mention
the Digilent Spartan-3 eval board. I briefly looked at the Virtex-5 data
sheet and it seems more likely that they actually used the Spartan-3.

The NW project page is grossly incomplete. The report is very promising,
but it only describes hardware (i.e., firmware). The new Oberon System is
absent from any description. Either it is described somewhere else, or it
has not been released (yet?).

This work at the firmware level is interesting. However, as usual in the
FPGA domain, it is already obsolete. For example, they use a soft SDRAM
controller, which is an appropriate solution for Spartan-3. The new
Spartan-6 has built-in hard SDRAM memory controllers. Therefore, a
substantial part of the firmware will need revisions for the newer FPGAs.
Such revisions will only be warranted if the software system (the compiler
etc) are available and of sufficient utility. It is not clear from the
report whether it is the case.

All in all very interesting, but not clear, if practically useful.

W

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Received on Sun Feb 19 2012 - 01:38:33 UTC