Re: [BLACKBOX] Project Oberon - FPGA

From: [at]} <Wojtek>
Date: Sun, 19 Feb 2012 09:39:35 -0500

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> > Interesting that he is using Verilog rather than LOLA.
> I was surprised as well, first I've read about it.
> He also has a speech, don't remember where, I guess at the google event
> in Zurich, where he shares his experience with the verilog toolchain. I
> mean, he didn't like the workflow.
> Why he has to use ready solution instead of writing it's own - I also do
> not understand. Not similar to what he usually does. So I wonder which
> are the reasons.

I said "interesting". I did not say "surprising". I am using VHDL which I
like better than Verilog, but it is also part of the same toolchain. One
can almost freely mix the two languages. My experience, like everyone
else's, is similar to NW's experience. But we have to either use the
manufacturer's toolchain, or some other vendor, which are all very similar
to one another.

In a nutshell, translation from the HDL into the "sea of gates" is such an
enormous problem that nobody wants to touch it except the manufacturer or
those vendors, who are in the same business. LOLA was conceived when the
programmable logic was relatively very simple. Not anymore. I heard of a
version of LOLA compiler which translated into EDIF, that is an
intermediate representation which the manufacturer's toolchain can
swallow. But this version was never released into the public.
Unfortunately, I guess.

I do not like Verilog look-and-feel, so I do not use it. I find VHDL
tolerable in a similar way as C++ is tolerable. One has to learn what NOT
to do. One has to develop one's own style and stick to it. Tricks and
smarts are the road to hell. Once I learned what not to do (I am still
learning), FPGA programming becomes one more task which is tractable.

Concerning the NW's work on the FPGA and the new Oberon System, it would
have been very interesting if it was released in full such that it could
be exercised. Not the case (yet?).

W.


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Received on Sun Feb 19 2012 - 15:39:35 UTC

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